Opcode 0xed
Possible values are 0 or a reference to one of the instruction operands. The EVEX b (broadcast/rounding control/suppress all exceptions context) bit. Always equals 0 in 32-bit x86 architecture. If vvvv is a reference to an instruction operand, the operand is of register type and EVEX.vvvv field encodes the register number. The value 0b0000 indicates that this field is not used. Possible values are 0b0000 or a reference to one of the instruction operands. Always equals 0b00 in 32-bit x86 architecture. If the rounding control operand is omitted, EVEX.L’L is set to 0b10 (embedded rounding control is only supported for 512-bit wide operations). Reference to the last instruction operand EVEX.L’L are interpreted as rounding control and set to the value specified by the operand. Possible values: None Indicates that the EVEX.L’L field is ignored. Specify either vector length for the operation, or explicit rounding control (in which case operation is 512 bits wide). Possible values are: 0b00 No implied prefix. The EVEX pp (compressed legacy prefix) field. 0b11 Implies 0x0F 0x3A leading opcode bytes. 0b10 Implies 0x0F 0x38 leading opcode bytes. Possible values are: 0b01 Implies 0x0F leading opcode byte. Identical to two low bits of VEX.m-mmmm field.
The EVEX mm (compressed legacy escape) field. The instruction operand has “moffs” type of the matching size.Įncoding may have only one EVEX prefix and if present, it immediately precedes the opcode, and no other prefix is allowed. Only MOV instruction has forms that use direct data offset. The instruction operand has “rel” type of the matching size.Ībsolute data offset embedded into instruction encoding. Must be a reference to an instruction operand. Offset is relative to the end of the instruction.
#Opcode 0xed code
Relative code offset embedded into instruction encoding.